1. Technical Field
The present invention relates to a level up shifter circuit.
2. Related Art
In the new-generation electronic circuit design, with introduction of low-voltage logic, a problem of input/output logic dissonance usually appears in the system, thereby increasing complexity of system design. A level up shifter circuit may be used in level conversion from a core voltage to an input/output (I/O) voltage.
FIG. 1 shows a conventional level up shifter circuit. When a voltage of an input end IN is a low level, an IXB is a high level, turning on a field effect transistor P1 and pulling down a level at a VA point, thereby turning on a field effect transistor N2, and then pulling up a level at a VB point; when the voltage of the input end IN is a high level, an IX is a high level, turning on a field effect transistor P2 and pulling down the level at the VB point, thereby turning on a field effect transistor N1, and then pulling up the level at the VA point. Through an inverter 101, levels at an output end OUT and the VB point are complementary to each other. Therefore, the level at the output end and the level at the input end basically synchronously change, and the change may be from a level range (for example, 1 v) of the input end IN to, for example, 3.3 v.
However, the circuit has a problem of long regeneration time, especially when VDDIO is much higher than VDDCORE, and this is caused by dragging of the speed of weak conduction of PMOS at the beginning of transition.
FIG. 2 shows another conventional level up shifter circuit. The circuit further includes some boost circuits, on the basis of FIG. 1, used for increasing the reaction speed of the level up shifter circuit. However, the boost circuits may be potentially stressed, because an NMOS gate voltage will be pulled up to be higher than VDDIO.
FIG. 3 shows still another conventional level up shifter circuit. The circuit further includes a level up shifter circuit, which is feasible in the presence of VDDMID. However, the circuit cannot be used in the absence of VDDMID.
In the above circuit, in the absence of VDDCORE, nodes VA and VB will present high impedance or be unknown. Therefore, the situation where an output state of the level up shifter circuit is unknown exists. The problem that the output state is unknown possibly arises when the core voltage is not ready or there is great phase imbalance between the core voltage and the IO voltage. The output state being unknown is dangerous in some applications (for example, hot swap), and this is because there may be a large inrush current flowing into/out of an I/O pin.